The present invention relates generally to phase-change memory cells.
Phase-change memory (PCM) is a non-volatile solid-state memory technology that exploits the reversible, thermally-assisted switching of phase-change materials, in particular chalcogenide compounds such as GST (Germanium-Antimony-Tellurium), between states with different electrical resistance. The fundamental storage unit (the “cell”) can be programmed into a number of different states, or levels, which exhibit different resistance characteristics. The s programmable cell-states can be used to represent different data values, permitting storage of information.
In single-level PCM devices, each cell can be set to one of s=2 states (a “SET” state and a “RESET” state) permitting storage of one bit per cell. In the RESET state, which corresponds to a wholly amorphous state of the phase-change material, the electrical resistance of the cell is very high. By heating the phase-change material to a temperature above its crystallization point and then cooling, the phase-change material can be transformed into a low-resistance, fully-crystalline state. This low-resistance state provides the SET state of the cell. If the cell is then heated to a high temperature, above the melting point of the phase-change material, the material reverts to the fully-amorphous RESET state on rapid cooling. In multilevel PCM devices, the cell can be set to s>2 programmable states permitting storage of more than one bit per cell. The different programmable states correspond to different relative proportions of the amorphous and crystalline phases within the volume of phase-change material. In particular, in addition to the two states used for single-level operation, multilevel cells exploit intermediate states in which the cell contains different volumes of the amorphous phase within the otherwise crystalline PCM material. Since the two material phases exhibit a large resistance contrast, varying the size of the amorphous phase within the overall cell volume produces a corresponding variation in cell resistance.
Reading and writing of data in PCM cells is achieved by applying appropriate voltages to the phase-change material via a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes Joule heating of the phase-change material to achieve an appropriate temperature to induce the desired cell-state on cooling. Reading of PCM cells is performed using cell resistance as a metric for cell-state. An applied read voltage causes current to flow through the cell, this current being dependent on resistance of the cell. Measurement of the cell current therefore provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that application of the read voltage does not disturb the programmed cell state. Cell state detection can then be performed by comparing the resistance metric with predefined reference levels for the s programmable cell-states.
A problem with phase-change memory is that the resistance of the amorphous phase exhibits undesirable attributes, such as low-frequency noise and drift. This drift causes resistance of the amorphous phase to increase in value over time. As a result, the read measurements for programmed cell states tend to change over time. This resistance drift complicates read out of the written information, potentially even destroying the information if there is a large variability in the amount of drift exhibited by different cell states so that the read measurement distributions for neighboring cell states interfere with one another. The larger the number of cell states and the closer the initial spacing between readback resistance levels, the more susceptible cells are to this problem. This presents a challenge in the development of multilevel phase-change memory efforts to achieve storage of more bits per cell for increased storage density and to reduce manufacturing cost per bit.
Currently, several techniques are used to alleviate problems associated with resistance drift. One class of techniques uses specialized read and write schemes for storage and readout of information in the memory. These techniques typically incur a penalty in write or read speed and require more complicated read/write circuitry for the memory cells. Another class of techniques makes use of coding to introduce redundancy in the stored information. This inherently reduces storage density. Another approach is disclosed in European Patent Application publication no. EP 2034536 A1 and illustrated in FIG. 1 of the accompanying drawings. This figure shows a schematic illustration of a PCM cell 1 having a volume of phase-change material 2 located between a top electrode 3 and a bottom electrode (or “heater”) 4. The cell state shown represents an intermediate state in which the material 2 contains both crystalline and amorphous phases. The amorphous phase is indicated by the shaded hemispherical volume 5 above bottom electrode 4. The crystalline phase 6 occupies the remainder of the cell volume. A thin resistive region 7 provides a parallel current path between the bottom electrode 4 and the crystalline phase 6 of the phase-change material in operation. When a read voltage is applied to read the programmed cell-state, the resulting cell current flows primarily via this current path from crystalline phase 6 to bottom electrode 4, in preference to flowing through the high-resistance amorphous phase 5. The resistance of the parallel current path depends on the length “x” in the figure.
Improved phase change memory cells is desirable.